The present invention relates to a semiconductor device, specifically to a semiconductor device provided with a DRAM (Dynamic Random Access Memory), for example.
For example, Patent Literature 1 discloses an NVSRAM in which a programmable transistor, such as an SONOS (Silicon Oxide Nitride Oxide Silicon) transistor, is combined with an SRAM (Static Random Access Memory) cell. Specifically, a source of the programmable transistor is coupled to one end of an information holding node of the SRAM via a transistor, and a drain is coupled to a power supply voltage via a transistor. The one end of the information holding node of the SRAM is coupled to the other end of the information holding node via an inverter Non-patent Literature 1 discloses a configuration in which a programmable transistor provided at the one end of the above-described information holding node is provided also at the other end, instead of the inverter of Patent Literature 1.
(Patent Literature 1) U.S. Pat. No. 8,792,275
(Non-patent Literature 1) Michael Fliesler, et al.; “A 15 ns 4 Mb NVSRAM in 0.13μ SONOS Technology”, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, pp. 83-86.